1. Field of the Invention
The present invention relates to a MOS transistor and a manufacturing method thereof by which a short channel phenomenon caused by miniaturization of the device is suppressed and high speed operation can be maintained.
2. Description of the Prior Art
With accelerated improvements in semiconductor manufacturing processes, devices such as MOS transistors have become miniaturized to on the order of a quarter micron in size. As a result, certain phenomena, including a short channel effect, can alter performance of devices.
The short channel effect refers to the reduction in transistor threshold voltage with reduced channel length. The threshold voltage of a small-sized transistor, i.e., channel length less than 0.4 xcexcm, decreases exponentially with decreasing channel length. The effect occurs because a shorter channel has a relatively larger portion of its active region affected by the drain voltage as compared to the portion under the influence of the gate voltage. The effect may be mitigated somewhat by defining the minimum transistor size to be larger than the size of the transistor having the minimally acceptable voltage threshold characteristics.
The short channel effect can be interpreted with a one-dimensional charge sharing model. Also, an accurate model for interpreting the short channel effect has been realized with numerical value analysis according to two-dimensional potential barrier lowering.
Various approaches to mitigating the short channel effect have been realized. For example, the thickness of the gate oxide layer, the maximum width of the depletion layer below the gate and the dopant density of the substrate can be decreased. Also, it is important to form a shallow junction to inhibit the effect.
Accordingly, a shallow ion implantation approach was introduced in the field of ultra large-scale integration (ULSI). Also, shallow junctions can be realized by using a rapid thermal annealing (RTA) process for heat treatment. As a result of these techniques, the short channel MOS transistor is taking preliminary steps to its introduction into mass production.
However, in spite of the introduction of the techniques for forming the shallow junction, the conventional techniques for the shallow junction are considered to have approached the limits of their applicability to high density, high integration devices in mass production, particularly as devices sizes approach a quarter-micron.
The conventional MOS transistor is generally modeled with a lightly doped drain (LDD) structure. Such an LDD structure is deposited on a moderate doped drain (MDD) in a shallow junction structure. The MDD structure compared with the LDD structure has enhanced the performance of the device by widenning a dopant level of the LDD region from 1xc3x971014/cm2 to 1xc3x971015/cm2. However, there is a problem in that the short channel effect according to short-channelization is mainly caused by the enhancement of the doping level in the MDD region.
Accordingly, the present invention is provided to solve the aforementioned problems and it is an object of the present invention to provide a MOS transistor with high-speed and high-performance operation and a manufacturing method thereof by which the short-channel effect caused by miniaturization of the device can be prevented.
In accordance with the present invention, there is provided a MOS transistor. The transistor of the invention includes a semiconductor substrate doped with a first conductivity type impurity, a gate insulating layer formed on the semiconductor substrate, gate electrodes formed on the gate insulating layer, and a dielectric layer formed on the gate electrode. A first spacer is formed around the gate electrodes, and a second spacer is formed on a first side wall of the first spacer. A first impurity layer of low concentration is formed at a first depth by a second conductivity type impurity implanted in the semiconductor substrate to be self-aligned at the edge of the gate electrode. A second impurity layer of middle concentration is formed in a deeper second depth than the first depth by the second conductivity type impurity implanted in the semiconductor substrate to be self-aligned at the edge of the first spacer. A third impurity layer having higher impurity concentration than that of the semiconductor is formed at a third depth for surrounding the second impurity layer of middle concentration by a first conductivity type impurity implanted in the semiconductor substrate to be self-aligned at the edge of the first spacer. A fourth impurity layer of high concentration is formed at a deeper fourth depth than the third depth by the second conductivity type impurity implanted in the semiconductor substrate to be self-aligned at the edge of the second spacer.
In addition, in accordance with another aspect, the present invention provides a method for manufacturing a MOS transistor. The method includes forming a gate insulating layer doped with a first conductivity type impurity, forming gate electrodes on the gate insulating layer, and forming a dielectric layer on the gate electrodes. The method further includes forming a first impurity layer of low concentration having a first depth by implanting a second conductivity type impurity in the semiconductor substrate to be self-aligned at the edge of the gate electrodes. A first spacer is formed on the side wall of the gate electrodes. A second impurity layer of middle concentration is formed at a deeper second depth than the first depth by implanting the second conductivity type impurity in the semiconductor substrate. A third impurity layer having higher impurity concentration than that of the semiconductor is formed at a third depth for surrounding the second impurity layer of middle concentration by implanting a first conductivity type impurity in the semiconductor substrate to be self-aligned at the edge of the first spacer. A second spacer is formed in the side wall of the first spacer, and a fourth impurity layer of high concentration is formed at a deeper fourth depth than the third depth by implanting the second conductivity type impurity in the semiconductor substrate to be aligned at the edge of the second spacer.